1. Field of the Invention
The present invention relates to a reference voltage circuit and an image-capture circuit, and more particularly, relates to a reference voltage circuit and an image-capture circuit which are configured to enable generation of a reference signal of low noise with a low consumption current.
2. Description of the Related Art
In CMOS (Complementary Metal Oxide Semiconductor) sensors which are a solid-state image capture element, CDS (Correlated Double Sampling) circuits have been used to process an image signal.
For example, Japanese Patent No. 3734717 or No. 3710361 discloses a CMOS sensor in which a received light signal from a photodiode in a pixel is caused to pass through an analog CDS circuit arranged per each pixel column, thereby removing noise included in the image signal, and thereafter, an A/D (Analog/Digital) conversion is performed.
However, when the CDS circuit is thus used, unevenness of the CDS circuit per each pixel column causes issues that noise of a fixed pattern having a stripe-shape is generated. Further, since a capacitative element for holding a signal value after CDS processing becomes necessary, there is an issue that a circuit area increases, and since an analog signal is caused to horizontally scan at high speed by a shift register, there is an issue that the circuit is susceptible to an influence, such as switching noise.
Therefore, in Japanese Patent Application Publication No. JP-2005-328135 (Patent Document 3), for example, there is proposed a parallel-column AD conversion system (hereinafter, referred to as a column AD system, where necessary).
In the column AD system, an A/D converter is arranged per each pixel column, and an analog signal of each pixel in the selection column is read out collectively to each vertical signal line and is subjected to A/D conversion directly. Thus, the issues caused when the above-described CDS circuit is used may be solved, permitting the execution of a highly accurate noise removal.
Further, in the column AD system, a parallel process is performed per each horizontal image row, and thus, it may not be necessary to drive scanning in the horizontal direction by a high-speed frequency and it is possible to drive the A/D conversion by a low-speed frequency in a vertical direction. The system also has an advantage in that a noise component generated in a high frequency band and a signal component may be easily separated.
In the CMOS sensor in which the column AD system is adopted, a reset component corresponding to a predetermine reference potential and a data component corresponding to an amount of light received of the pixel are included in the pixel signal supplied from the pixel to the A/D converter. The A/D converter is supplied with a ramp signal (ramp voltage) which is a signal referred to when the pixel signal is subjected to A/D conversion. The ramp signal is a signal of a waveform in which voltage drops from a predetermined initial voltage at a certain gradient during a time period corresponding to the reset component of the pixel signal and in which voltage drops from a predetermined initial voltage at a certain gradient during a time period corresponding to the data component of the pixel signal.
FIG. 1 is a block diagram showing a reference voltage circuit for generating a ramp signal to be supplied to the A/D converter of the CMOS sensor.
In FIG. 1, the reference voltage circuit 11 includes a constant current source array 12, a constant current source selection unit 13, a resistance 14, and an output terminal 15.
The constant current source array 12 includes a gain-change constant current source 16, an offset-change constant current source 17, and n of ramp-waveform generation constant current sources 181 to 18n.
The gain-change constant current source 16, the offset-change constant current source 17, and the ramp-waveform generation constant current sources 181 to 18n constitute a current mirror (CM). One end of the offset-change constant current source 17 and one ends of the ramp-waveform generation constant current sources 181 to 18n are connected to the output terminal 15. The other end of the offset-change constant current source 17 is grounded and the other ends of the ramp-waveform generation constant current sources 181 to 18n are connected to the constant current source selection unit 13.
The output terminal 15 is connected via the resistance 14 to a reference voltage Vref. From the reference voltage Vref, the ramp signal of voltage is generated in response to a change in current outputted from the constant current source array 12, and outputted from the output terminal 15.
When a gain of an image captured by the CMOS sensor is changed, the gain-change constant current source 16 is supplied with a control signal from a control circuit (not shown), and a current value of the gain-change constant current source 16 is changed in response to the control signal, thereby changing the gradient of the ramp signal.
The offset-change constant current source 17 is supplied with the control signal from the control circuit (not shown) when offsetting an initial voltage of the ramp signal of a time period corresponding to the reset component of the pixel signal and an initial voltage of the ramp signal of a time period corresponding to the data component of the pixel signal. The current value of the offset-change constant current source 17 is changed in response to the control signal, and the initial voltage of the ramp signal is offset.
The ramp-waveform generation constant current sources 181 to 18n are selected by the constant current source selection unit 13, and output a current for generating the gradient of the ramp signal.
The constant current source selection unit 13 sequentially selects the current source from which the current should flow, out of the ramp-waveform generation constant current sources 181 to 18n, in response to a clock from the control circuit (not shown).
In the reference voltage circuit 11 configured as above, the reference voltage Vref connected to the resistance 14 is used as a reference, and the ramp signal which changes according to the current outputted from the constant current source array 12 is generated.
Thus, in addition to generating the ramp signal in which the reference voltage Vref is used as a reference, a ramp signal in which GND is used as a reference by supplying the current to the resistance connected to the output terminal and the GND, for example may be generated.
That is, FIG. 2 is a block diagram showing other example of the reference voltage circuit for generating the ramp signal.
In FIG. 2, a reference voltage circuit 11′ includes a constant current generating circuit 20, three transistors 21 to 23, a gain change circuit 24, a transistor 25, a ramp generating circuit 26, an offset circuit 27, and a resistance 28.
One end of the constant current generating circuit 20 is grounded, and the other end of the constant current generating circuit 20 is connected to a drain of the transistor 21. A source of the transistor 21 is connected to a power supply voltage VDD, and a gate of the transistor 21 is connected to a gate of the transistor 22. A connection point between the gate of the transistor 21 and the gate of the transistor 22 is connected to a connection point between the constant current generating circuit 20 and the drain of the transistor 21.
A source of the transistor 22 is connected to a power supply voltage VDD, and a drain of the transistor 22 is connected to a drain of the transistor 23.
A gate of the transistor 23 is connected to the gain change circuit 24, and a connection point between the gate of the transistor 23 and the gain change circuit 24 is connected to a connection point between the drain of the transistor 22 and the drain of the transistor 23. A source of the transistor 23 is grounded.
The gain change circuit 24 is a circuit for changing the gradient of the ramp signal when the gain of the image captured by the CMOS sensor is changed. Further, the gain change circuit 24 and the transistor 23 constitute a current mirror circuit.
A drain of the transistor 25 is connected to the gain change circuit 24, a source of the transistor 25 is connected to a power supply voltage VDD, and a gate of the transistor 25 is connected to the ramp generating circuit 26. A connection point between the drain of the transistor 25 and the gain change circuit 24 is connected to a connection point between the gate of the transistor 25 and the ramp generating circuit 26.
The ramp generating circuit 26 is a circuit for generating the gradient of the ramp signal. The ramp generating circuit 26 is grounded via the resistance 28.
The offset circuit 27 is a circuit for offsetting the initial voltage of the ramp signal of a time period corresponding to the reset component of the pixel signal and the initial voltage of the ramp signal of a time period corresponding to the data component of the pixel signal. The offset circuit 27 is connected to a connection point between the ramp generating circuit 26 and the resistance 28, and this connection point is connected to an output terminal (not shown) of the ramp signal.
A description is made for voltage noise caused to the ramp signal by the constant current generating circuit 20, the transistors 21 to 23, the gain change circuit 24, the transistor 25, the ramp generating circuit 26, and the offset circuit 27, in the reference voltage circuit 11′ configured as above.
Voltage noise VN0 caused by the constant current generating circuit 20 to the ramp signal is represented by the following equation (1):VN0=in0×(gm2/gm1)×(gm4/gm3)×(gm6/gm5)×Rout  (1)
In the equation (1), in0 denotes current noise of the constant current generating circuit 20, gm1 denotes a voltage amplification ratio of the transistor 21, gm2 denotes a voltage amplification ratio of the transistor 22, and gm3 denotes a voltage amplification ratio of the transistor 23. Further, gm4 denotes a voltage amplification ratio of the gain change circuit 24, gm5 denotes a voltage amplification ratio of the transistor 25, gm6 denotes a voltage amplification ratio of the ramp generating circuit 26, gm7 denotes a voltage amplification ratio of the offset circuit 27, and Rout denotes a resistance value of the resistance 28.
When voltage noise of the transistor 21 is represented as vn1, voltage noise VN1 caused by the transistor 21 to the ramp signal is expressed by the following equation (2):VN1=vn1×gm2×(gm4/gm3)×(gm6/gm5)×Rout  (2)
When VN2 denotes voltage noise caused by the transistor 22 to the ramp signal, VN3 denotes voltage noise caused by the transistor 23 to the ramp signal, VN4 denotes voltage noise caused by the gain change circuit 24 to the ramp signal, VN5 denotes voltage noise caused by the transistor 25 to the ramp signal, VN6 denotes voltage noise caused by the ramp generating circuit 26 to the ramp signal, and VN7 denotes voltage noise caused by the offset circuit 27 to the ramp signal, total noise VN caused to the ramp signal is expressed by the following equation (3):VN2=VN02+VN12+VN22+VN32+VN42+VN52+VN62+VN72  (3)
As expressed in the equation (3), in the reference voltage circuit 11′, the voltage noises VN0 to VN7 are superposed on the total noise VN generated in the ramp signal. In the reference voltage circuit 11′, since there are many noise sources of the voltage noise, it is difficult to reduce the total noise VN. Further, as shown from the equations (1) to (3), when a return ratio (mirror ratio) in the current mirror circuit which is constituted of the gain change circuit 24 and the transistor 23 (for example, gm4/gm3) becomes large, the total noise VN also becomes large.
A current consumption of the reference voltage circuit 11′ is a total of currents flowing in the current mirror from an initial stage to an output stage. That is, the current consumption of the reference voltage circuit 11′ is totals of a current I0 which flows in the constant current generating circuit 20, a current I1 which flows in the transistor 23, a current I2 which flows in the gain change circuit 24, and a current I3 which flows in the resistance 28.
As described above, in the reference voltage circuit 11′, there are many stages of current paths, and thus, it is difficult to reduce the current consumption.